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Integrated Circuit Systems, Inc.
ICS9250-32
Frequency Generator & Integrated Buffers for PII/IIITM
Recommended Application: Timna Style Chipset Output Features: * 3 - CPUs @ 2.5V * 8 - PCI @ 3.3V * 2 - IOAPIC @ 2.5V * 1 - MREF @ 2.5V, DRCG memory reference clock * 9 - SDRAM @ 3.3V including one free running * 1 - 2V48M @ 2.5V fixed (DOT) * 1 - 3V48M @ 3.3V fixed (USB) * 2 - REF @ 3.3V, 14.318MHz. Features: * Support power management: CPU, PCI, SDRAM stop from I2C programming. * Spread spectrum for EMI control (0 to -0.5%) * Uses external 14.318MHz crystal Key Specifications: * CPU Output Jitter (Cyc-Cyc): <175ps * IOAPIC Output Jitter (Cyc-Cyc): <500ps * MREF Output Jitter (Cyc-Cyc): <250ps * 2V48M Output Jitter (Cyc-Cyc): <250ps * 3V48M Output Jitter (Cyc-Cyc): <500ps * CPU - CPU: < 175ps * SDRAM - SDRAM < 250ps * PCI - PCI: < 500ps * IOAPIC - IOAPIC: < 250ps * BUFFER_IN to SDRAM prop delay: 5.5 to 7.5ns
Pin Configuration
2V48M 3V48M VDD48 GND48 X1 X2 GND *(CPU2_EN#)REF0 REF1 VDD PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDDPCI GNDPCI PCICLK6 PCICLK7 SCLK VDDA GNDA SDATA BUF_IN *FS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDLIOAPIC IOAPIC0 IOAPIC1 GNDLIOAPIC VDDLCPU CPUCLK0 CPUCLK1 VDDLCPU GNDLCPU CPUCLK2 MREF66 VDD SDRAM_F SDRAM0 VDDSDR GNDSDR SDRAM1 SDRAM2 SDRAM3 GNDSDR VDDSDR SDRAM4 SDRAM5 VDDSDR GNDSDR SDRAM6 SDRAM7 FS1*
56-Pin 300mil SSOP
* These inputs have a 50K pull up to VDD.
Functionality
FS1 FS0 1 1 0 1 0 Power up Latched REF1/CPU2_EN# 1 0 X X X CPU0 CPU1, MREF 66MHz 66MHz TCLK/2 Reserved Tristate CPU2 Tristate 66MHz TCLK/2 Reserved Tristate
Block Diagram
PLL2 3V48M 2V48M X1 X2 XTAL OSC PLL1 Spread Spectrum BUF_IN CPU_EN# SDATA SCLK FS (1:0) Control Logic Config. Reg.
PCI DIVDER
8
1 1
2
REF (1:0)
1
CPU DIVDER
3
CPUCLK (2:0)
0 0
SDRAM DIVDER
8
SDRAM (7:0) SDRAM_F
IOAPIC DIVDER
2
IOAPIC (1:0)
Power Groups
VDD = REF, X1, X2 VDDPCI = PCICLK VDDSDR = SDRAM VDD48 = 3V48M VDDLCPU = CPU VDDLIOAPIC = IOAPIC, 2V48M VDDA = PLL Core
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
PCICLK (7:0)
3V66 DIVDER
MREF66
9250-32 Rev B 9/7/00 Third party brands and names are the property of their respective owners.
ICS9250-32
ICS9250-32
General Description
The ICS9250-32 is the single chip clock solution for Desktop designs. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-32 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER 1 2 3, 10, 14, 19, 24, 33, 36, 42, 45 4, 7, 13, 20, 25, 32, 37, 41, 48, 53 5 6 8 9 22, 21, 18, 17, 16, 15, 12, 11 23 26 27 28 29 30, 31, 34, 35, 38, 39, 40, 43 44 46 49, 52, 56 47, 50, 51 54, 55 PIN NAME 2V48M 3V48M VDD GND X1 X2 CPU2_EN# REF0 REF1 PCICLK (7:0) SCLK SDATA BUF_IN FS0 FS1 SDRAM (7:0) SDRAM_F MREF66 VDDL CPUCLK (2:0) IOAPIC (1:0) TYPE OUT OUT PWR PWR IN OUT IN OUT OUT OUT IN I/O IN IN IN OUT OUT OUT PWR OUT OUT DESCRIPTION 48MHz output clock 2.5V (DOT) clock 48MHz output clock 3.3V (USB) clock 3.3V Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 3V48 output Ground pins Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Disables CPU2 when pulled high (default) Enables CPU2 when pulled Low 14.318 MHz reference clock. 14.318 MHz reference clock. PCI clock outputs. Clock pin of I C circuitry 5V tolerant Data pin for I C circuitry 5V tolerant Input to fan out buffer for SDRAM Frequency select pin. Frequency select pin. SDRAM clock outputs SDRAM clock output free running not affected by I C DRCG reference memory 2.5V 66MHz Power pins for CPUCLKs, and IOAPIC clocks. 2.5V 2.5V CPU clock outputs. 2.5V IOAPIC clock outputs
2 2 2
Functionality
FS1 1 1 1 0 0 FS0 1 1 0 1 0 Power up Latched CPU0 REF1/CPU2_EN# CPU1,MREF 1 66MHz 0 66MHz X TCLK/2 X Reserved X Tristate CPU2 Tristate 66MHz TCLK/2 Reserved Tristate SDRAM [0:7] BUF_IN BUF_IN BUF_IN Reserved Tristate 2V48: 3V48 48MHz 48MHz TCLK/2 Reserved Tristate PCI 33MHz 33MHz TCLK/4 Reserved Tristate REF IOAPIC
14.318MHz 33MHz 14.318MHz 33MHz TCLK TCLK/4 Reserved Reserved Tristate Tristate
Third party brands and names are the property of their respective owners.
2
ICS9250-32
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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3
ICS9250-32
Byte 0: Active/Inactive Control Register (1= enable, 0 = disable) Byte 1: Active/Inactive Control Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 1 2 -
PWD 0 0 0 0 0 1 1 1
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d Spread Spectrum (0=On/1=Off 2V48M (DOT) 3V48M (USB) R e s e r ve d
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 30 31 34 35 38 39 40 43
PWD 1 1 1 1 1 1 1 1
DESCRIPTION SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 2: Active/Inactive Control Register (1= enable, 0 = disable)
Byte 3: Active/Inactive Control Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 22 21 18 17 16 15 12 11
PWD 1 1 1 1 1 1 1 1
DESCRIPTION PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
BIT PIN# PWD Bit 7 0 Bit 6 <> Bit 5 <> Bit 4 <> Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Note:
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Byte 4: Active/Inactive Control Register (1= enable, 0 = disable)
<>, with these 3 bits, the registers will store the written values. The read back, however, will be the invert of the written value.
BIT PIN# PWD Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
Notes:
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
4
ICS9250-32
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND 0.5 V to V DD +0.5 V 0C to +70C 115C 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 2 VDD+0.3 Input High Voltage VIH VSS-0.3 0.8 Input Low Voltage VIL VIN = VDD -5 5 Input High Current IIH VIN = 0 V; Inputs with no pull-up resistors -5 IIL1 Input Low Current VIN = 0 V; Inputs with pull-up resistors -200 IIL2 IDD3.3OP CL = Max loads;Select @ 66 MHz 251 280 Operating Supply Current IDD2.5OP CL = Max loads;Select @ 66 MHz 27 100 VDD = 3.3 V 14.312 Input Frequency Fi CIN Logic Inputs 5 Input Capacitance X1 & X2 oins 27 45 CINX Transition time1 Settling time Clk Stabilization1 Skew1
1 1
UNITS V V A A mA mA MHz pF pF ms ms ms ns ns
Ttrans Ts
To 1st crossing of target frequency From 1st crossing to 1% target frequency 1.5 1.5 2.3 2.1
3 3 3 3.5 3.5
TSTAB From VDD = 3.3 V to 1% target frequency TCPU-IOAPIC CPU & IOAPIC @ 1.25 V TCPU-PCI CPU @ 1.25 V, PCI @ 1.5 V
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
ICS9250-32
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 RDSP2B VO = VDD*(0.5) Output Impedance RDSN2B VO = VDD*(0.5) Output Impedance1 IOH = -1 mA VOH2B Output High Voltage VOL2B IOL = 1 mA Output Low Voltage VOH @ MIN = 1.0 V IOH2B Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL2B Output Low Current VOL @ MAX = 0.3 V 1 tr2B VOL = 0.4 V, VOH = 2.0 V Rise Time Fall Time
1 1 1 1
MIN 11.5 11.5 2
-27 27 0.4 0.4 45
TYP 14 16 2.5 0.011 -79 -10 66 20 1.1 1.1 47 54 140
MAX UNITS 45 45 V 0.4 V -27 mA mA ns ns % ps ps
30 1.6 1.6 55 175 250
tf2B dt2B tsk2B tjcyc-cyc2B
VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
Duty Cycle
Skew window
1
Jitter, Cycle-to-cycle
Guaranteed by design, not 100% tested in production. AC timing of the trise & tfall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of transition time target.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP1B VO = VDD*(0.5) Output Impedance1 RDSN1B VO = VDD*(0.5) Output High Voltage VOH1 IOH = -1 mA Output Low Voltage VOL1 IOL = 1 mA VOH @ MIN = 1.0 V IOH1 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL1 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 11 11 2.4
-27 29 0.5 0.5 45
TYP 14 13 3.29 0.009 -111 -12 96 31 1.2 1.4 51 212 230
MAX UNITS 55 55 V 0.55 V -29 mA mA ns ns % ps ps
27 2 2 55 500 500
tr1 tf1 dt1 tsk1 tjcyc-cyc1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
AC timing of the trise & tfall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of transition time target.
Third party brands and names are the property of their respective owners.
6
ICS9250-32
Electrical Characteristics - 2V48M
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 RDSP5 VO = VDD*(0.5) Output Impedance RDSN5 VO = VDD*(0.5) Output Impedance1 IOH = -1 mA VOH5 Output High Voltage IOL = 1 mA VOL5 Output Low Voltage VOH @ MIN = 1.0 V IOH5 Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL5 Output Low Current VOL @ MAX = 0.3 V 1 tr5 VOL = 0.4 V, VOH = 2.0 V Rise Time Fall Time
1 1 1
MIN 9.5 9.5 2
TYP
-27 27 0.4 0.4 45
2.5 0.007 -93 -11 81 27 0.7 0.7 53 180
MAX UNITS 45 45 V 0.4 V -27 mA mA ns ns % ps
30 1.6 1.6 55 250
tf5 dt5 tjcyc-cyc5
VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
Duty Cycle
1
Jitter, Cycle-to-cycle
Guaranteed by design, not 100% tested in production. AC timing of the trise & tfall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of transition time target.
Electrical Characteristics - 3V48M
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-15 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP5 VO = VDD*(0.5) Output Impedance1 RDSN5 VO = VDD*(0.5) Output High Voltage VOH5 IOH = -1 mA Output Low Voltage VOL5 IOL = 1 mA VOH @ MIN = 2.0 V IOH5 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL5 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 16 16 2.4
TYP 24 3.3 0.014 -65 -8 65 21 1.2 1.6 54 290
-23 29 0.5 0.5 45
MAX UNITS 60 60 V 0.4 V -27 mA mA ns ns % ps
27 2 2 55 500
tr5 tf5 dt5 tjcyc-cyc5
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, CPU=66,100,133 MHz
Duty Cycle Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production. AC timing of the trise & tfall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of transition time target.
Third party brands and names are the property of their respective owners.
7
ICS9250-32
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP2A VO = VDD*(0.5) Output Impedance1 RDSN2A VO = VDD*(0.5) Output High Voltage VOH2A IOH = -1 mA Output Low Voltage VOL2A IOL = 1 mA VOH @ MIN = 2.0 V IOH2A Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL2A Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1 1
MIN 8.5 8.5 2.4
-46 53 0.4 0.4 45 5.5
TYP 10.1 12 3.3 0.006 -100 -13 90 40 1 0.8 51 212 6.5
MAX UNITS 24 24 V 0.4 V -54 mA mA ns ns % ps ns
54 1.6 1.6 55 250 7.5
tr2A tf2A dt2A tsk2A tsk2B
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
Duty Cycle
Skew (ouput to output) Skew (Buffer In to output)1
1
Guaranteed by design, not 100% tested in production. AC timing of the trise & tfall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of transition time target.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-15 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance1 RDSP5 VO = VDD*(0.5) Output Impedance1 RDSN5 VO = VDD*(0.5) Output High Voltage VOH5 IOH = -1 mA Output Low Voltage VOL5 IOL = 1 mA VOH @ MIN = 2.0 V IOH5 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V IOL5 Output Low Current VOL @ MAX = 0.4 V Rise Time1 Fall Time
1 1
MIN 16 16 2.4
-23 29
TYP 24 19.2 3.3 0.014 -65 -8 65 21 1.4 1.4
MAX UNITS 60 60 V 0.4 V -27 mA mA ns ns % ps
27 4 4 55 1000
tr5 tf5 dt5 tjcyc-cyc5
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, CPU=66,100,133 MHz 45
Duty Cycle Jitter, Cycle-to-cycle1
1
54 674
Guaranteed by design, not 100% tested in production. AC timing of the trise & tfall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of transition time target.
Third party brands and names are the property of their respective owners.
8
ICS9250-32
Electrical Characteristics - MREF66
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 RDSP2B VO = VDD*(0.5) Output Impedance 1 RDSN2B VO = VDD*(0.5) Output Impedance IOH = -1 mA VOH2B Output High Voltage IOL = 1 mA VOL2B Output Low Voltage VOH @ MIN = 1.0 V IOH2B Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL2B Output Low Current VOL @ MAX = 0.3 V 1 tr2B VOL = 0.4 V, VOH = 2.0 V Rise Time Fall Time
1 1 1
MIN 11.5 11.5 2
-27 27 0.4 0.4 45
TYP 14 16 2.5 0.011 -79 -10 66 20 1.1 1.1 47 168
MAX UNITS 45 45 V 0.4 V -27 mA mA ns ns % ps
30 1.6 1.6 55 250
tf2B dt2B tjcyc-cyc2B
VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
Duty Cycle
1
Jitter, Cycle-to-cycle
Guaranteed by design, not 100% tested in production. AC timing of the trise & tfall is controlled by pre-driver circuit which allows lower impedance output to stay in the middle of transition time target.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP4B VO = VDD*(0.5) VO = VDD*(0.5) Output Impedance RDSN4B1 IOH = -1 mA Output High Voltage VOH4B IOL = 1 mA Output Low Voltage VOL4B VOH @ MIN = 1.0 V IOH4B Output High Current VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V IOL4B Output Low Current VOL @ MAX = 0.3 V Rise Time1 Fall Time
1 1
MIN 13.5 13.5 2
-27 27 0.4 0.4 45
TYP 16 19 2.5 0.013 -68 -9 54 20 1.2 0.95 48 18 93
MAX UNITS 45 45 V 0.4 V -27 mA mA ns ns % ps ps
30 1.6 1.6 55 250 500
tr4B tf4B dt4B tsk1 tjcyc-cyc4B
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V, IOIAPIC=PCI/2 VT = 1.25 V VT = 1.5 V VT = 1.25 V
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9250-32
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS925032 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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10
ICS9250-32
SY MBOL
In Millimeters COMMON DIMENSIONS MIN MA X 2.413 0.203 0.203 2.794 0.406 0.343
In Inc hes COMMON DIMENSIONS MIN MA X .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N V A RIA TIONS N 28 34 48 56 64
0.127 0.254 SEE V A RIA TIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE V A RIA TIONS .395 .291 .015 .420 .299 .025
0.635 BA SIC 0.508 1.016 SEE V A RIA TIONS 0 8
0.025 BA SIC .020 .040 SEE V A RIA TIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MA X 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inc h) MA X .380 .455 .630 .730 .830
6/1/00 R E VB
J EDE C MO- 118 DOC# 10- 0034
Ordering Information
ICS9250yF-32-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
11
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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